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1 of 15 012207 special features ? 1,152-bit secure read /write, nonvolatile memory ? secure memory cannot be deciphered without matching 64-bit password ? memory is partitioned into 3 blocks of 384 bits each ? 64-bit password and id fields for each memory block ? 512-bit scratchpad ensures data transfer integrity ? operating temperature range: -40c to +70c ? over 10 years of data retention common i button features ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike ? multidrop controller for microlan ? digital identification and information by momentary contact ? chip-based data carrier compactly stores information ? data can be accessed while affixed to object ? economically communicates to bus master with a single digital signal at 16.3 kbits per second ? standard 16 mm diameter and 1-wire ? protocol ensure compatibility with i button ? family ? button shape is self-aligning with cup- shaped probes ? durable stainless steel case engraved with registration number withstands harsh environments ? easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim ? presence detector acknowledges when reader first applies voltage ? meets ul#913 (4th edit.); intrinsically safe apparatus, approved under entity concept for use in class i, division 1, group a, b, c and d locations f5 microcan io gnd 0.51 5.89 16.25 17.35 a1 02 000000fbc52b 1-wire ? ? ? all dimension\s shown in millimeters ordering information ds1991l-f5 f5 microcan examples of accessories ds9096p self-stick adhesive pad ds9101 multi-purpose clip ds9093ra mounting lock ring ds9093f snap-in fob ds9092 i button probe ds1991 multikey i button www.ibutton.com 1-wire and i button are registered trademarks of dallas semiconductor. downloaded from: http:///
ds1991 2 of 15 i button description the ds1991 multikey i button is a rugged read/write data carrier that acts as three separate electronic keys, offering 1,152 bits of secure, nonvolatile memory. e ach key is 384 bits long with distinct 64-bit password and public id fields (figure 1). the passwor d field must be matched in order to access the secure memory. data is transferred serially via the 1- wire protocol, which requires only a single data lead and a ground return. the 512-b it scratchpad serves to ensu re integrity of data tran sfers to secure memory. data should first be written to the sc ratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to th e secure memory. this pro cess ensures data integrity when modifying the memory. a 48-b it serial number is factory lase red into each ds1991 to provide a guaranteed unique identity which allo ws for absolute traceability. the family code for the ds1991 is 02h. the durable microcan package is hi ghly resistant to environmental hazar ds such as dirt, moisture and shock. its compact button-shaped pr ofile is self-aligning with mating receptacles, allowing the ds1991 to be easily used by human operators. accessories perm it the ds1991 to be mounted on plastic key fobs, photo-id badges, printed-circuit boards or any smoot h surface of an object. appl ications include secure access control, debit tokens, work-in-progress trac king, electronic travelers and proprietary data. operation the ds1991 is accessed via a single data line usi ng the 1-wire protocol. th e bus master must first provide one of the four rom func tion commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom. these commands operate on the 64-bit lasered rom portion of each device and can singulate a specific device if many are present on the 1-wire line as well as indicate to the bus master how many and what types of devices are present. the prot ocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functions that operate on the secure memory and the scratc hpad become accessible and the bus master may issue any one of the six memory function commands speci fic to the ds1991. the prot ocol for these memory function commands is described in fi gure 5. all data is read and writte n least significant bit first. 64-bit lasered rom each ds1991 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (figure 2.) the 1-wire crc is generated using a polynomial generato r consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire cyclic redundancy check is available in the book of ds19xx i button standards. the shift register bits are initialized to zero. then starting with the least si gnificant bit of the family code, 1 bit at a time is shifted in. after the 8th bit of the family code has b een entered, then the serial number is entered. after the 48th bit of the serial number has been entered, th e shift register contains the crc value. shifting in the 8 bits of crc should return th e shift register to all zeros. memory function commands the ds1991 has six device-specific commands. three scratchpad commands: write scratchpad, read scratchpad and copy scratchpad and three subkey commands: write password, write subkey and read subkey. after the device is selected, the memory function command is written to the ds1991. the command is comprised of three fields, each one byte l ong. the first byte is the function code field. this field defines the six commands that can be executed. the second byte is the address field. the first 6 bits of this field define the starting address of the command. the last 2 bits of this field are the subkey address code. the third byte of the command is a co mplement of the second byte (figure 4). downloaded from: http:///
ds1991 3 of 15 for the first use, since the passwords actually st ored in the device are unknown, the ds1991 needs to be initialized. this is done by direct ly writing (i. e., not through the scratchpad) the new identifier and password for the selected subkey using the write password command. as soon as the new identifier and password are stored in the device, further upd ates should be done through the scratchpad. memory map figure 1 * each subkey or the scratchpad has its own unique address. 64-bit lasered rom figure 2 8-bit crc code 48-bit serial number 8-bit family code (02h) msb lsb msb lsb msb lsb 1-wire crc generator figure 3 downloaded from: http:///
ds1991 4 of 15 ds1991 command structure figure 4 2 nd byte 3 rd byte command 1 st byte b7 b6 b5 b4 b3 b2 b1 b0 write scratchpad 96h read scratchpad 69h 1 1 any value 00h to 3fh copy scratchpad 3ch 0 0 0 0 0 0 read subkey 66h write subkey 99h any value 10h to 3fh write password 5ah sub-key nr.: 0 0 or 0 1 or 1 0 0 0 0 0 0 0 ones complement of 2 nd byte scratchpad commands the 64-byte read/write scratchpad of the ds1991 is not password-protecte d. its normal use is to build up a data structure to be verified a nd then copied to a secure subkey. write scratchpad [96h] the write scratchpad command is used to enter data into the scratchpad. the starting address for the write sequence is specified in the command. data can be continuously written until the end of the scratchpad is reached or until the ds1991 is reset. the command sequence is shown in figure 5, first page, left column. read scratchpad [69h] the read scratchpad command is used to retrieve data from the scratchpad. the starting address is specified in the command word. data can be continuously read until the end of the scratchpad is reached or until the ds1991 is reset. the command sequence is shown in figure 5, first page, center column. copy scratchpad [3ch] the copy scratchpad command is used to transfer specifi ed data blocks from the scratchpad to a selected subkey. this command should be used when data veri fication is required befo re storage in a secure subkey. data can be transferred in si ngle 8-byte blocks or in one large 64-byte bloc k. there are nine valid block selector codes that are used to specify which block is to be tr ansferred (figure 6). as a further precaution against accidental erasure of secure data, the 8-byte password of the destination subkey must be entered. if the password does not match, the operation is terminated. after the block of data is transferred to the secure subkey, th e original data in the corresponding block of the scratchpad is erased. the command sequence is shown in fi gure 5, first page, right column. subkey commands each of the subkeys within the ds1 991 is accessed individuall y. transactions to read and write data to a secured subkey start at the address defined in the command and proceed until th e device is reset or the end of the subkey is reached. downloaded from: http:///
ds1991 5 of 15 write password [5ah] the write password command is used to enter the id and password of the selected subkey. this command will erase all of the data stored in the secu re area as well as overwriting the id and password fields with the new data. the ds1991 has a built-in ch eck to ensure that the proper subkey was selected. the sequence begins by reading the id field of the selected subkey; the id of the subkey to be changed is then written into the part. if the ids do not match, the sequence is terminated. otherwise, the subkey contents are erased and 64 bits of new id data are written followed by a new 64-bit password. the command sequence is shown in figure 5, 2nd page, right column. memory functions flow chart figure 5 downloaded from: http:///
ds1991 6 of 15 memory functions flow chart (contd) figure 5 downloaded from: http:///
ds1991 7 of 15 block selector codes of the ds1991 figure 6 block nr. address range ls byte codes ms byte 0 to 7 00 to 3fh 56 56 7f 51 57 5d 5a 7f 0 identifier 9a 9a b3 9d 64 6e 69 4c 1 password 9a 9a 4c 62 9b 91 69 4c 2 10h to 17h 9a 65 b3 62 9b 6e 96 4c 3 18h to 1fh 6a 6a 43 6d 6b 61 66 43 4 20h to 27h 95 95 bc 92 94 9e 99 bc 5 28h to 2fh 65 9a 4c 9d 64 91 69 b3 6 30h to 37h 65 65 b3 9d 64 6e 96 b3 7 38h to 3fh 65 65 4c 62 9b 91 96 b3 write subkey [99h] the write subkey command is used to enter data into the selected subkey. since the subkeys are secure, the correct password is required to access them. th e sequence begins by reading the id field; the password is then written back. if the password is inco rrect, the transaction is terminated. otherwise, the data following is written into the secure area. the starting address for the write sequence is specified in the command word. data can be continuously written until the end of the secu re subkey is reached or until the ds1991 is reset. the command sequence is shown in figure 5, 2nd page, center column. read subkey [66h] the read subkey command is used to retrieve data from the selected subkey. since the subkeys are secure, the correct password is required to access th em. the sequence begins by r eading the id field; the password is then written back. if the password is incorrect, the ds1991 will transmit random data. otherwise the data can be read from the subkey. the starting address is specified in the command. data can be continuously read until the end of the subkey is reached or until the ds1991 is reset. the command sequence is shown in figure 5, 2nd page, left column. 1-wire bus system the 1-wire bus is a system which has a single bus ma ster and one or more slaves. in all instances, the ds1991 is a slave device. the bus mast er is typically a micro-controller or pc. for small configurations the 1-wire communication signals can be generated under software contro l using a single port pin. for multisensor networks, the ds2480b 1-wire line driver ch ip or serial port adapters based on this chip (ds9097u series) are recommended. this simplifies the hardware design and frees the microprocessor from responding in real-time. the discussion of this bus system is broken down in to three topics: hardware configuration, transaction sequence, and 1-wire signaling (signa l types and timing). a 1-wire protoc ol defines bus tr ansactions in terms of the bus state during specifie d time slots that are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a si ngle line by definition; it is important that each devi ce on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have an open drain connections or tri-state ou tputs. the 1-wire port of the ds19 91 is an open drain part with an internal circuit equivalent to that shown in figure 7. the bu s master can be the same equivalent circuit. if a bidirectional pin is not availa ble, separate output and input pins can be tied together. downloaded from: http:///
ds1991 8 of 15 the bus master requires a pullup resistor at the ma ster end of the bus, with the bus master circuit equivalent to the one shown in figures 8a a nd 8b. the value of the pullup resistor should be approximately 5 k for short line lengths. a multidrop bus consists of a 1-wire bus with multip le slaves attached. the 1-wire bus has a maximum data rate of 16.3 kbits per second. the idle state for the 1-wire bus is hi gh. if, for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur, and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. downloaded from: http:///
ds1991 9 of 15 equivalent circuit figure 7 bus master circuit figure 8 downloaded from: http:///
ds1991 10 of 15 transaction sequence the protocol for accessing the ds1991 via the 1-wire port is as follows: ? initialization ? rom function command ? memory or sha function command ? transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus ma ster followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds1991 is on the bus and is ready to operate. for more details, see the 1-wire signaling section rom function commands once the bus master has detected a presence pulse, it can issue one of the four rom function commands that the ds1991 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 9). read rom [33h] this command allows the bus master to read the ds 1991s 8-bit family code, unique 48-bit serial number and 8-bit crc. this command should only be used if there is a single ds1991 on the bus. if more than one slave is present on the bus, a data collision will o ccur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the result ant family code and 48-bit serial number read by the master will be invalid. match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds1991 on a multidrop bus. only the ds1991 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit rom c ode. if more than one slave is present on the bus and, for example, a read command is issued follow ing the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneou sly (open drain will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64 -bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple 3-step routine: read a bit, read the comp lement of the bit, then write the desired value of that bit. the bus master performs th is simple 3-step routine on each bit of the rom. after one complete pass, the bus master knows the c ontents of the rom in one device. additional passes will identify the rom codes of the remaining devices.. downloaded from: http:///
ds1991 11 of 15 1-wire signaling the ds1991 requires strict protocols to ensure data integrity. the prot ocol consists of four types of signaling on one line: reset sequen ce with reset pulse and presence pulse, write 0, write 1 and read data. all these signals except presence pulse are ini tiated by the bus master. the initialization sequence required to begin any communication with the ds1991 is shown in figur e 10. a reset pulse followed by a presence pulse indicates the ds1991 is ready to se nd or receive data given the correct rom command and memory function command. the bus mast er transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. afte r detecting the rising edge on the data pin, the ds1991 waits (t pdh , 15-60 s) and then transmits the presence pulse (t pdl , 60-240 s). rom functions flow chart figure 9 downloaded from: http:///
ds1991 12 of 15 initialization procedure r eset and prese nce pulses figure 10 480 s t rstl < * 480 s t rsth < (includes recovery time) 15 s t pdh < 60 s 60 s t pdl < 240 s ? in order not to mask interrupt signali ng by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. read/write time slots the definitions of write and read time slots are illu strated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds1991 to the master by triggering a delay circuit in th e ds1991. during write time slots, the delay circuit determines when the ds1991 will sample the data line. for a read data time sl ot, if a 0 is to be tr ansmitted, the delay circuit determines how long the ds1991 will hold the data line low overriding the 1 generated by the master. if the data bit is a 1, the i button will leave the read data time slot unchanged. read/write timing diagram figure 11 write-one time slot 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < resistor master resistor master ds1991 downloaded from: http:///
ds1991 13 of 15 read/write timing diagram (contd) figure 11 write-zero time slot 60 s < t low0 < t slot < 120 s 1 s < t rec < read-data time slot 6 0 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s resistor master ds1991 downloaded from: http:///
ds1991 14 of 15 physical specifications size see mechanical drawing weight 3.3 grams expected service life 10 years at 25 c (150 million transactions, see note 4) safety meets ul#913 (4th edit.); intrinsically safe apparatus, approved under entity concept for use in class i, division 1, group a, b, c and d locations absolute maxi mum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature -40c to +70c storage temperature -40c to +70c ? this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the opera tion sections of this specifica tion is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. dc electrical characteristics (v pup *=2.8v to 6.0v; -40 c to +70 c) parameter symbol min typ max units notes input logic low v il -0.3 0.8 v 1 input logic high v ih 2.2 6.0 v output logic low @ 4 ma v ol 0.4 v output logic high v oh v pup 6.0 v 1,2 input resistance v il 500 k 3 * v pup = external pullup voltage ac electrical characteristics (-40c to 70c) parameter symbol min typ max units notes time slot period t slot 60 120 s write 1 low time t low1 1 15 s write 0 low time t low0 60 120 s read data valid t rdv exactly 15 s release time t release 0 15 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset low time t rstl 480 s reset high time t rsth 480 s 4 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s downloaded from: http:///
ds1991 15 of 15 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage to system supply. 3. input pulldown resistance to ground. 4. an additional reset or communication sequence ca nnot begin until the rese t high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge a nd will remain valid for 14 s minimum. (15 s total from falling edge on 1-wire bus.) downloaded from: http:///

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